IBM and Samsung unveil semiconductor milestone

IBM and Samsung unveil semiconductor milestone

17 December 2021 | Natalie Bannerman

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IBM and Samsung Electronics have hailed a breakthrough in semiconductor design using a new vertical transistor architecture.

The new design demonstrates the potential to scaling beyond nanosheet and has the ability to reduce energy usage by 85% compared to a scaled fin field-effect transistor (finFET).

The new comes amid the global semiconductor shortage which has highlighted the need for investment in chip research and development as well as the importance of chips in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

Produced at the Albany Nanotech Complex in Albany, New York, the new vertical transistor breakthrough could help the semiconductor industry continue to deliver significant improvements. These include, mobile phone batteries that could go over a week without being charged; energy intensive processes, such as cryptomining operations and data encryption, could require significantly less energy and have a smaller carbon footprint; as well as the continued expansion of IoT and edge devices with lower energy needs.

"Today's technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact," Dr Mukesh Khare, vice president of hybrid cloud and systems at IBM Research.

"Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call 'hard tech.'"

Traditionally transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them. With new Vertical Transport Field Effect Transistors (VTFET), IBM and Samsung have implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow. 

Using this VTFET process addresses performance barriers and limitations to extend Moore's Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy.

Overall, the new design aims to deliver a two times improvement in performance or an 85% reduction in energy use as compared to scaled finFET alternatives.